Peak Performance Projection

Quantitative projection of 1bit systems end-state throughput on Strix Halo (Ryzen AI MAX+ 395) once all seven planned lanes ship. Every number has a derivation or a citation. All projections carry a ±20% band unless stated otherwise.

0. Fixed constants

1. Current ceiling per surface (measured 2026-04-20)

Bandwidth-bound ceiling on the ternary GEMV today: 256 GB/s ÷ 630 MB/tok ≈ 406 tok/s theoretical. Measured 83 tok/s @ L=64 means the reachable roofline after amortizing KV + attn + sampler is ~85–90 tok/s — consistent with Benchmarks.md. At L=1024 the KV-cache dominates: 33 tok/s × 92% × 256 GB/s ≈ 7.1 GB read per token, essentially all KV.

2. Decode ceiling math

Formula: tok/s ≤ (BW × util) / (W_bytes × actsparse_factor) where util = 0.92 from the rocprof roofline.

The 83 → ~280 tok/s path is compounding on a bandwidth-bound stack: every lane that shrinks bytes-per-token lifts the same wall. Medusa multiplies on top because it issues ≥2 tokens per weight-read pass.

3. Prefill ceiling (compute-bound, NPU wins)

Prefill per-token FLOPs (fwd, attn + FFN, BitNet-2B):

F/tok ≈ 2 × (4·h² + 3·h·ffn) × layers
      = 2 × (4·2560² + 3·2560·6912) × 30
      = 2 × (26.2M + 53.1M) × 30
      ≈ 4.76 GFLOPs/tok

Crossover L\* where NPU total time beats iGPU total time, solving t_npu_oh + L/npu_tps = t_igpu_oh + L/igpu_tps:

L* = (3ms − 0.2ms) / (1/5000 − 1/8800)
   = 2.8e-3 / (2.00e-4 − 1.14e-4)
   = 2.8e-3 / 8.6e-5
   ≈ 33 tokens

NPU beats iGPU at prefill beyond ~33 tokens. For realistic chat prompts (128–2048 in) the NPU is the right surface unconditionally. Uncertainty band: 25–60 tokens depending on actual BD-list setup cost (IRON #93 has no live timing yet).

4. All-surfaces-parallel latency (512-in + 256-out)

TTFT ≈ 70 ms, total wall ≈ 1.23 s for 512+256. Today the same workload is ~4.1 s (prefill on iGPU, decode bottleneck). Projected wall-clock improvement: ~3.3× end-to-end.

5. End-to-end decode tok/s ceiling (2B model, L=64)

The 280 tok/s headline number assumes (a) Sherry packs to 1.25 bits with no PPL regression >0.1, (b) BitNet v2 a4 KV is bit-exact vs fp16 KV on our re-pack path, (c) Medusa 1.7× accept rate on our workload (lower than MedusaBitNet's reported 2.3× because our baseline is already faster).

6. The bandwidth wall

Even at 280 tok/s decode with every lane shipping, the final ceiling is the LPDDR5-8000 controller. Derivation of the wall:

theoretical max = 256 GB/s × 0.92 util / (0.35 GB/tok best-case)
               ≈ 673 tok/s

Medusa multiplies tokens-per-weight-fetch by 1.7×, which is the only way past ~400 tok/s on this bus. Beyond that you need:

• DDR6 (consumer, ~2027): 512–768 GB/s → linear 2–3× lift.
• HBM3 (not coming to Ryzen AI APUs — Strix Halo's LPDDR5 is soldered).
• On-die SRAM residency (Cerebras territory — not applicable to 2B

at batch=1).

For the 2026-04 Strix Halo box, 256 GB/s is the terminal ceiling. Everything we ship between now and DDR6 is bytes-per-token reduction.

Sources

• Live measurements: Benchmarks.md, benchmarks/bench.sh,

benchmarks/ppl-gen2.sh, benchmarks/attn_fd.sh.

• NPU hardware: IRON #55 (column count,

TOPS), IRON #93 (INT8 kernel), PR #94.

• Model: Microsoft BitNet b1.58,

BitNet v2.

• Memory notes: project_bitnet_live_bench.md, project_sherry_spike.md,

project_activation_sparsity_phase1.md, project_attention_fd.md, project_npu_path_analysis.md.

One-line homepage summary

Projected ceiling: ~280 tok/s decode + NPU prefill crossover at ~33 tokens once all seven lanes ship, at the 256 GB/s LPDDR5 wall.